This application claims priority to International Application No. PCT/DE00/00392 which was published in the German Language on Aug. 31, 2000.
The invention relates to a method and a circuit arrangement for the time-critical routing of data to a clocked interface with asynchronous data transmission.
In existing and future communication, systems, in particular communications systems operating according to the asynchronous transfer mode (ATM), data is and will be transmitted in a cell stream formed from cells or IP (Internet Protocol) packets. Specifically in the case of communications systems which operate according to the asynchronous transfer mode, the ATM layer model is used for functionally dividing the communications tasks, the ATM layer model being composed, like the OSI (Open Systems Interconnection) reference model from a plurality of communications layers which are independent of one another. These include the physical layer, the ATM layer, the ATM adaptation layer (AAL) and the user-oriented layers designated as xe2x80x9chigher layersxe2x80x9d in the OSI terminology. The function of a layer is to make available services for the next higher layer. In particular, the physical layer makes available a transmission interface for the cells of the superordinate ATM layer. This interface has been defined by the ATM forum as a uniform, clocked interface between the physical layer and the higher layers of communications devices which operate according to the asynchronous transfer mode, the interface being known in the specialist field by the name xe2x80x9cUniversal Test and Operation PHY-interface for ATMxe2x80x9d or xe2x80x9cUtopiaxe2x80x9d for shortxe2x80x94see in particular ATM Forum, Level 2, v1.0, June 1995, pages 8-15 and 21-24.
In this UTOPIA Level 2 interface which is standardized by the ATM Forum, during the routing of the data to the interface very critical signaling occurs which gives rise to a number of technical implementation problems, particularly in the upstream direction, i.e. from the physical interfacexe2x80x94also referred to as secondary sidexe2x80x94to the communications systemxe2x80x94also called primary side. Inter alia, the UTOPIA specification requires, for example, setup times of at least 4 nsec for a 50 MHz UTOPIA interface and hold times of at least 1 nsec. Owing to these setup and hold time requirements, all the signaling signals must be sampled at the input end immediately in order to be able to initiate the reaction to the signaling signals in the subsequent clock period, i.e. the signaling between the primary side and the secondary side is very time-critical. Furthermore, the standardized UTOPIA Level 2 interface standardizes a plurality of different complex signaling operations, the processing of which requires a complex control logic owing to their number. The implementation of such rapid reaction times and the implementation of the required complex control logic requires suitable hardware support, i.e. high speed logic modules such as ASICs (Application Specific Integrated Circuit) or high speed, small FPGAs (Field Programmable Gate Array) with short, internal signal transit times.
In the case of the standardized UTOPIA Level 2 interface, in particular the xe2x80x9cMultiphysicalxe2x80x9d UTOPIA Level 2, there is additionally provision for a plurality of physical interfaces to be connected to the ATM layer, which requires address decoding and control with respect to the physical layer which is to be addressed. Furthermore, the previously described complexity of the different signaling operations in the case of a xe2x80x9cmultiphysicalxe2x80x9d operation of the UTOPIA interface is considerably increased, i.e. a complex and time-critical routing and decoding logic is necessary for the time-critical routing of data from a plurality of physical layers to the one ATM layer owing to the large number of different complex signaling operations and the selection of the physical layer which is authorized to transmit data in each case.
The invention relates to a method and a circuit arrangement for the time-critical routing of data to a clocked interface with asynchronous data transmission, there being parallel transmission of data between a physical layer, or at least one physical layer, and a further layer in accordance with a standardized layer model, of a ready signal which is generated by the physical layer and which indicates or does not indicate a data transmission request, and of a release/blocking signal which is generated by the further layer in order to route the data transmission and/or if appropriate of a plurality of address signals which are generated by the further layer. In addition, a reaction to a change in the release/blocking signal or in the ready signal occurs within at least one clock period.
In one embodiment of the invention, there is time-critical routing of the data to a clocked interface with asynchronous data transmission, in particular the interface between a physical layer, or between a plurality of physical layers, and the ATM layer.
In one aspect of the invention, the release/blocking signal is indicated to the physical layer delayed by one clock period, and the data to be transmitted in parallel is routed a priori to the clocked interface by the physical layer, and a reload signal for routing the data to the interface in a suitably timed and clocked fashion is generated by a logic connection of the delayed release/blocking signal and of the ready signal which is generated by the physical layer. The delaying of the release/blocking signal which is generated by the further layer and the subsequent logic connection of the delayed release/blocking signal to the ready signal which is generated by the physical layer enables very short reaction times to be obtained in different signaling operations. As a result, the number of the signaling scenarios or cases standardized by the ATM Forum is reduced to one case, i.e. the different time-critical signaling operations which occur during the operation of the interface are processed by the method according to the invention using a single, simple control logic. This means that no additional cost-intensive, high speed logic modules such as FPGAs for implementing a complex control logic are necessary to implement the method according to the invention but instead simple standard logic modules such as gates and flipflops can be used. In particular, the signaling requirements of future UTOPIA standards which are already in planning, for example UTOPIA Level 3 xe2x80x94see ATM Forum PHY WG, UTOPIA Level 3 Baseline Text, December 1998xe2x80x94with maximum clock rates of virtually 104 MHz and data bus widths of 32 bits can be advantageously realized using the method according to the invention, especially since in the field it is considered impractical to realize a complex control logic which is necessary to implement the UTOPIA Level 2 and 3 Standard without the method according to the invention with logic functions which are currently available in ASICs or high speed, small FPGAs owing to the extremely short signal transit times which are required.
According to another embodiment of the invention, when there is a reload signal which indicates a data transmission, further data is routed to the interface, and when there is a reload signal which indicates no data transmission, the currently present data and no further data is routed to the interface. As a result, data is routed to the interface in a particularly advantageous way after the transmission of the currently present data by the delayed release or blocking signal has already taken place, i.e. further data is routed to the interface immediately after the transmission of the currently present data. In addition, this ensures that no data can be reloaded from the physical layer to the clocked interface without a ready signal which indicates a data request or a reload signal which indicates a data release.
The logic connection of the delayed release/blocking signal and of the ready signal generated by the decentralized device is advantageously carried out according to the invention by means of a logic AND connection. A logic AND connection constitutes a xe2x80x9chigh speedxe2x80x9d logic connection and can be implemented easily, i.e. without a large degree of expenditure on circuitry.
One advantage of the invention is that the data to be transmitted is routed a priori to the clocked interface by the physical layer without a data transmission release of the physical layer being indicated by the further layer using the release/blocking signal. As a result of premature routing of the data to be transmitted to the interface by the physical layer, data is already present a priori at the interface, i.e. from the point of view of the physical layer data is already being transmitted. However, ultimately the delayed release/blocking signal directly brings about a data transmission, i.e. when a release/blocking signal which indicates a data transmission is present the currently present data is transmitted and further data is routed to the interface. The invention thus complies with the reaction time required for data to be applied to the interface after reception of the release and blocking signal which indicates a data transmission.
Another aspect of the invention is the fact that the release/blocking signal is indicated to the physical layer delayed by at least one clock period, and that the address signals are delayed by at least one clock period and the ready signal which is to be indicated to the further layer at a given time is selected by reference to the delayed address signals and routed to the interface. Furthermore, the data which is to be transmitted in parallel is routed from the respective physical layer to the clocked interface a priori and as a function of the address signals and the release/blocking signal, and immediately sampled. In addition, at least one first and one second reload signal for routing the data to the interface in a suitably timed and clocked fashion are generated by respective logic connections of the delayed release/blocking signal and of the delayed address signals for a physical layer in each case. As a result of the delaying of the release/blocking signal generated by the further layer, and of the address signals, very short reaction times are obtained for different signaling operations, especially since, when the release/blocking signal does not signal a data transmission, the physical layer which is authorized for transmission at a given time is determined by reference to the address signals which are present, and said physical layer directly routes its first data byte to the interface. The data, currently selected on the basis of the address signals, of the respective physical layer is thus directly present at the interface, as a result of which the short reaction times which are required by the UTOPIA interface standard can be realized. As a result, the multiplicity of signaling scenarios or cases which are standardized by the ATM Forum is reduced to a small number of cases, i.e. the different, time-critical signaling operations which occur during the operation of the interface and the selection of the respective physical layer are processed the invention using a single simple routing and decoding logic. This means that, in order to implement the invention, no cost-intensive, high speed logic modules, such as high speed ASICs or small, high speed FPGAs are necessary to implement a complex routing and decoding logic, but rather it is possible to use simple, cost-effective, relatively slow ASICs or FPGAs. In particular, the signaling requirements of future UTOPIA standards which are already in planning, for example MPHY-UTOPIA Level 3xe2x80x94see ATM Forum PHY WG, UTOPIA Level 3 Baseline Text, December 1998xe2x80x94with maximum clock rates of virtually 104 MHz and data bus widths of 32 bits can be advantageously implemented using the method according to the invention, especially since an implementation of a complex control logic which is necessary to implement the UTOPIA level 2 and 3 Standard, in particular in the case of xe2x80x9cmultiphysicalxe2x80x9d operation is considered to be impractical in the specialist field without the method according to the invention with logic functions which are currently available in ASICs or high speed, small FPGAs, owing to the extremely short signal transit times which are required.
According to still another embodiment of the invention, when there is a first reload signal which indicates a data transmission previously stored data is routed to the interface, and when there is a second reload signal which indicates a data transmission further data is routed to the interface. Furthermore, when there is a first or second reload signal which indicates no data transmission, the currently present data and no further data is routed to the interface, and data is routed to the interface either using the first or the second reload signal. As a result, the data to be transmitted is routed to the interface in a particularly advantageous way, in particular after the transmission of the currently present data by the delayed release/blocking signal has already taken place, i.e. further data is routed to the interface immediately after the transmission of the currently present data. In addition, this ensures that no data is reloaded from the physical layer to the clocked interface without a ready signal which indicates a data request or a first or second reload signal which indicates a data release. Furthermore, data which has already been stored in a memory unit is advantageously routed by the first reload signal, i.e. for example the first data word or data byte of an ATM cell, or the cell start signal which is present, is buffered in a memory unit in the current clock cycle and read out in the next clock cycle if requested and routed directly to the interface. In this way, data which is required in the next clock period and is no longer currently present can be particularly advantageously routed at short notice to the interface, as a result of which, for example, the loss of a data byte or of an information item which is present in the current clock period but is required at a given time is avoided.
The logic connections of the delayed release/blocking signal and of the delayed and decoded address signals for a physical layer in each case is advantageously carried out according to the invention using a decoding unitxe2x80x94i.e. the embodiment can be implemented without a large degree of expenditure on circuitry. Furthermore, the signal transit times are kept short by implementing the decoding unit on a single logic level.
Another advantage of the invention is that data, to be transmitted, of the physical layer selected by reference to the address signals is routed a priori to the clocked interface from the respective physical layer without the further layer indicating a data transmission release for the respective physical layer using the release/blocking signal by reference to the address signals generated by the further layer for addressing the respective physical layer. By virtue of the premature routing of the data to be transmitted from the respective physical layer to the interface, data is already present a priori at the interface, i.e. from the point of view of the respective physical layer data is already being transmitted; but the delayed release/blocking signal directly brings about a data transmission, i.e. when a release/blocking signal which indicates a data transmission is present, the data which is currently present is transmitted and further data is routed to the interface. The invention thus ensures the short reaction time which is required for the application of data of the physical layer defined by the address signals to the interface after reception of the release/blocking signal which indicates a data transmission.